Secure Digital (SD) is a standard for nonvolatile memory cards, which may be used in portable devices such as mobile phones and tablet computers. The Secure Digital standard is maintained by the SD Association (SDA).
The SD standard includes an Ultra High Speed, Phase I (UHS-I) bus design for Secure Digital High-Capacity (SDHC) cards and Secure Digital eXtended-Capacity (SDXC) cards. UHS-I is a design enhancement to increase the performance of SDHC and/or SDXC cards.
UHS-I specification defines two bus architecture options supporting up to 50 MB/s (UHS-50) and 104 MB/s (UHS-104) data transfer rates respectively. According to the UHS-I specification, a host provides the memory card with a peripheral clock. UHS-50 supports a peripheral clock frequency of 100 MHz, and UHS 104 supports a peripheral clock frequency of up to 208 MHz. In at least one mode, four bits are transferred over four lines when a data clock signal rises and another four bits on the same four lines when the data clock signals falls, transferring an entire byte on each full clock cycle. UHS-II further raises the data transfer rate to a theoretical maximum of 156 MB/s (full duplex) or 312 MB/s (half duplex) using additional row of pins.
The various supported clock frequencies are theoretic maximums. The actual clock frequencies additionally vary, for example, based on Process, Voltage, and Temperature (PVT).
A controller may handle communication between the host and the nonvolatile memory card. A loop delay in the controller may be the time between when a request for data is received by the controller and when the data is first provided on a bus to the host. The loop delay may include time to retrieve the data from the nonvolatile memory card, delays from logic components of the controller, and even pad delays in an interface with the bus.
The loop delay may vary significantly. For example, the loop delay may vary significantly across PVT (Process, Voltage, and Temperature). In addition, different hosts may provide peripheral clocks that operate at different frequencies. Due to the variance in the loop delay and peripheral clock frequencies, the data may be provided on the bus on or near a transition of the peripheral clock, which may result in the host incorrectly reading the data.